1. Field of the Invention
The present invention relates generally to semiconductor memory cells and, more particularly, to a semiconductor memory cell capable of preventing excessive power consumption.
2. Description of the Background Art
FIG. 9 is a block diagram illustrating an example of a conventional dynamic random access memory (hereinafter referred to as a DRAM) which is generally known. Referring to FIG. 9, the DRAM includes a memory array 58 provided with memory cells for storing a data signal, an address buffer 54 for receiving an address signal for selecting a memory cell, a row decoder 55 and a column decoder 56 for decoding the address signal, and a sense amplifier 63 connected to memory array 58 for amplifying and reading the signal stored in the memory cell. An input buffer 59 for inputting a data signal and an output buffer 60 for outputting a data signal are connected through an I/O gate 57 to memory array 58.
Address buffer 54 is provided to receive external address signals ext.A0 to A9 or internal address signals Q0 to Q8 generated by a refresh counter 53. A refresh controller 52 drives refresh counter 53 in response to timing of a RAS signal and a CAS signal applied to a clock generator 51.
An RAS buffer 64 is provided in clock generator 51, and an activation signal S is applied therefrom through a sense amplifier controller 65 to a sense amplifier 63.
FIG. 10A is a cross sectional view of a memory cell included in a memory array 58 illustrated in FIG. 9, and FIG. 10B is an equivalent circuit diagram of the memory cell.
Referring to FIG. 10A, a memory cell includes a storage capacitor 16 formed on a main surface of a P-type semiconductor substrate 13 for storing a charge and an access transistor 17 provided adjacent to storage capacitor 16. Storage capacitor 16 includes an N-type impurity region 14 formed on the main surface of semiconductor substrate 13 to be a storage node and a cell plate 15 formed on N-type impurity region 14 with an insulating film interposed therebetween. Access transistor 17 includes N-type diffusion layers 14, 18 to be source/drain regions and a gate electrode 12 to be a word line formed between N-type diffusion layers 14 and 18 with the insulating film interposed therebetween. A bit line 11 is connected to N-type diffusion layer 18 to be a source/drain region. A memory cell is separated from an adjacent memory cell using a field oxide film 19.
Now, operations of writing into the memory cell and reading from the memory cell will be described with reference to FIGS. 10A and 10B.
In the case of writing, data to be written is externally transmitted to bit line 11, then the potential of word line 12 is raised to Vcc or more, a potential of storage node 14 implemented with an N-type diffusion region formed in P-type substrate 13 becomes Vcc (a high or "H" level) or GND (a low or "L" level), and a charge is stored in storage capacitor 16 formed of storage node 14 and cell plate 15. In the case of reading, the potential of word line 12 is raised, and the charge stored in storage node 14 is applied to bit line 11 and amplified by the sense amplifier. Respective memory cells are separated from one another by a SiO.sub.2 film servina as the field insulating film.
Storage node 14 is connected to the source of access transistor 17 so that a little leak current flows from the PN junction through a parasitic diode 20 to the substrate. The potential of P-type substrate 13 is normally kept at a negative potential by a power supply 21 in a DRAM, so that the potential of storage node 14 in which "H" level is written is lowered by electrons (indicated by arrow A) flowing from the substrate as time passes. Therefore, in a DRAM, it is necessary to perform rewriting referred to as "a refresh operation" every predetermined time. This will be described with reference to FIGS. 11A, 11B and 12 in the following.
FIG. 11A is a typical diagram illustrating a specific arrangement of memory array 58 in the general DRAM illustrated in FIG. 10, FIG. 11B is a diagram illustrating details of sense amplifier 2, and FIG. 12 is a timing diagram for explaining the refresh operation. The refresh operation is the same operation as reading in which the potential of a word line 12 is selectively raised at time t1, and storage nodes 14 of a plurality of memory cells 1 connected thereto are electrically connected to bit lines 11 charged to a precharge level. After a charge stored in storage capacitor 16 of each memory cell 1 is discharged onto a bit line 11, sense amplifier 2 is activated by activation signals .phi.SA1, .phi.SA2 at time t2. The potential of bit line 11 is amplified to the Vcc level or the GND level, and that potential is applied to storage node 14. Then, the potential of word line 12 is lowered at time t3. With this operation, it is possible to make the potential of the storage node to be kept at "H" level, which was lowered by the leak current, recover to Vcc as illustrated in FIG. 12(e).
Now, the current consumed in the refresh operation will be calculated in the following. First, the charge Q.sub.BL necessary for charging bit line 11 is expressed by an expression Q.sub.BL =(1/2)V.sub.cc .times.C.sub.BL .times.N, wherein C.sub.BL expresses the stray capacitance of the bit line, and N expresses the number of bit lines activated by one refresh operation.
Besides, a charge of Q.sub.P is consumed in the address buffer, a word line driving circuit, and so on. Furthermore, a current of I.sub.0 is always consumed in a substrate voltage generating circuit for applying a negative potential to P-type substrate 13 and so on regardless of the refresh operation. Finally, if the frequency of the refresh operation is expressed by f.sub.ref, the mean current I.sub.ref in the refresh operation is expressed by an expression EQU I.sub.ref =(Q.sub.BL +Q.sub.P).multidot.f.sub.ref +I.sub.o ( 1).
The ratio of the first term of expression (1) to the second term of it is: in a case where f.sub.ref is 64 kHz, for example, (Q.sub.BL +Q.sub.P).multidot.f.sub.ref is approximately 450 .mu.A, and I.sub.o is approximately 50 .mu.A, and the ratio is approximately 9:1.
Since there is only a PN junction between a P-type substrate and an N-type diffusion region in a storage node of a memory cell in a conventional DRAM, electrons flow from the substrate into the storage node to lower the potential of the storage node. Therefore, a refresh operation is necessary for holding data. However, the refresh operation is complicated and consumes excessive power for every refresh operation.